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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56603/D DSP56603 Advance Information 16-BIT DIGITAL SIGNAL PROCESSOR The DSP56603 is designed specifically for low-power digital cellular subscriber applications and can perform a wide variety of fixed-point digital signal processing algorithms. The DSP56603 is a member of the DSP56600 core family of 16-bit programmable CMOS Digital Signal Processors (DSPs). The DSP56600 core can execute one instruction per clock cycle. This 60-MHz chip is optimized for processing-intensive, yet cost-effective, low power consumption digital mobile communications applications. Because the DSP56603 provides on-chip Program and data RAM, as well as the ability to switch sections of this memory between program and data memory, it is also suitable for use as a development platform. Figure 1 provides a block diagram of the DSP56603, showing the core structures and the expansion areas. The DSP56600 core includes the Data Arithmetic and Logic Unit (ALU), Address Generation Unit (AGU), Program Controller, Program Patch Detector, Bus Interface Unit, On-Chip Emulation (OnCETM) module, JTAG port, and a Phase Lock Loop (PLL)-based clock generator. The expansion areas provide the switchable program and data memories, as well as a versatile set of on-chip peripherals and external ports. 3 16 6 6 Triple Timer or GPIO pins Dedicated GPIO pins Host Interface HI08 or GPIO pins SSI Interface or GPIO pins Bootstrap ROM 3072 x 24 Program RAM 16.5 K x 24 Memory Expansion Area X Memory RAM 8192 x 16 XM_EB Y Memory RAM 8192 x 16 YM_EB PIO_EB PM_EB Peripheral Expansion Area GDB Address Generation Unit Program Patch Detector YAB XAB PAB 16 Address External Bus Interface 4 Control 24 Data YDB Internal Data Bus Switch Clock Generator PLL PCAP CLKOUT RESET 16-bit DSP56600 Core XDB PDB Power Management Program Interrupt Controller Program Decode Controller MODA/IRQA Program Address Generator Data ALU 16 x 16 + 40 40-bit MAC Two 40-bit Accumulators 40-bit Barrel Shifter 5 JTAG OnCETM DE EXTAL PINIT/NMI MODB/IRQB MODC/IRQC MODD/IRQD AA0529 Figure 1 DSP56603 Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. (c)1996 MOTOROLA, INC. Table of Contents TABLE OF CONTENTS SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 APPENDIX A SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . A-1 DATA SHEET CONVENTIONS This data sheet uses the following conventions: OVERBAR "asserted" "deasserted" Examples: This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL Note: 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. ii DSP56603/D, Preliminary MOTOROLA Data Sheet Conventions DSP56603 FEATURES Digital Signal Processing Core * * * * * * * * * * * * * * * High-performance DSP56600 core Up to 60 Million Instructions Per Second (MIPS) at 2.7-3.3 V Fully pipelined 16 x 16-bit parallel Multiply-Accumulator (MAC) Two 40-bit accumulators including extension bits 40-bit parallel barrel shifter Highly parallel instruction set with unique DSP addressing modes Code-compatible with the DSP56300 core Position-independent code support User-selectable stack extension Nested hardware DO loops Fast auto-return interrupts On-chip support for software patching and enhancements On-chip Phase Lock Loop (PLL) circuit Real-time trace capability via external address bus On-Chip Emulator (OnCE) module and JTAG port Memory * Switch Mode memory allows reconfiguring program, X-data, and Y-data RAM sizes - Switch Mode off * * * - 16.5 K x 24-bit Program RAM 8 K x 16-bit X-data RAM 8 K x 16-bit Y-data RAM 11.5 K x 24-bit Program RAM 10.5 K x 16-bit X-data RAM 10.5 K x 16-bit Y-data RAM Switch Mode on * * * * 3 K x 24-bit bootstrap ROM MOTOROLA DSP56603/D, Preliminary iii Data Sheet Conventions * * Off-chip expansion for both program fetch and program data transfers No additional logic needed for interface to external SRAM memories Peripheral Circuits * * Three dedicated General Purpose Input/Output (GPIO) pins and as many as thirtyone additional GPIO pins (user-selectable as peripherals or GPIO pins) Host Interface (HI08) support: one 8-bit parallel port (or as many as sixteen additional GPIO pins) - - * Direct interface to Motorola HC11, Hitachi H8, 8051 family, Thomson P6 family Minimal logic interface to standard ISA bus, Motorola 68K family, and Intel x86 microprocessor family. Synchronous Serial Interface (SSI) support: two 6-pin ports (or twelve additional GPIO pins) - - - - Supports serial devices with one or more industry-standard codecs, other DSPs, microprocessors, and Motorola SPI-compliant peripherals Independent transmitter and receiver sections and a common SSI clock generator Network mode using frame sync and up to 32 time slots 8-bit, 12-bit, and 16-bit data word lengths * * * Three programmable timers (or as many as three additional GPIO pins) Three external interrupt/mode control lines One external reset pin for hardware reset Energy Efficient Design * Very low power CMOS design - - - * * * Operating voltage range: 1.8 V to 3.3 V < 0.85 mA/MIPS at 2.7 V < 0.55 mA/MIPS at 1.8 V Low power Wait for interrupt standby mode, and ultra low power Stop standby mode Fully static, HCMOS design for operating frequencies from 60 MHz down to DC Special power management circuitry iv DSP56603/D, Preliminary MOTOROLA For the Latest Information PRODUCT DOCUMENTATION The three documents listed in Table 1 are required for a complete description of the DSP56603 and are necessary to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 1 DSP56602 Chip Documentation Topic DSP56600 Family Manual DSP56603 User's Manual DSP56603 Technical Data Description Detailed description of the 56600-family architecture, and 16-bit DSP core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the DSP56603 Electrical and timing specifications, pin descriptions, and package descriptions Order Number DSP56600FM/AD DSP56603UM/AD DSP56603/D FOR THE LATEST INFORMATION Refer to the back cover of this document for: * * * * Motorola contact addresses Motorola MfaxTM service Motorola DSP Internet address Motorola DSP Helpline The Mfax service and the DSP Internet connection maintain the most current specifications, documents, and drawings. These two services are available on demand 24 hours a day. MOTOROLA DSP56603/D, Preliminary v SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS INTRODUCTION The input and output signals of the DSP56603 are organized into functional groups, as shown in Table 1-1 and as illustrated in Figure 1-1. In Table 1-2 through Table 1-12, each table row describes the signal or signals present on a pin. The DSP56603 is operated from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 1-1 Functional Group Signal Allocations Functional Group Power (VCC) Ground (GND) PLL and Clock Signals Interrupt and Mode Control External Memory Port (also referred to as Port A) Address Bus Data Bus Bus Control Host Interface (HI08) Port B (GPIO) Synchronous Serial Interface 0 Port C (GPIO) (SSI0) Synchronous Serial Interface 1 Port D (GPIO) (SSI1) General Purpose Input/Output (GPIO) Triple Timer JTAG/On-Chip Emulation (OnCE) Module Number of Signals 19 19 5 5 16 24 4 16 6 6 3 3 6 Table 1-7 Table 1-8 Table 1-9 Table 1-10 Table 1-11 Table 1-12 Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 MOTOROLA DSP56603/D, Preliminary 1-1 Signal/Connection Descriptions Introduction DSP56603 VCCA VCCC VCCD VCCH VCCP VCCQH VCCQL VCCS GNDA GNDC GNDD GNDH GNDP GNDP1 GNDQ GNDS 3 4 Power Inputs: Address Bus Bus Control Host Interface Data Bus (HI08) Port1 HI08 PLL Port B Internal Logic High-voltage Internal Logic Low-voltage SSI/GPIO/Timer Grounds: Address Bus Bus Control Data Bus HI08 PLL PLL Internal Logic SSI/GPIO/Timer 8 3 4 2 4 4 4 HAD0-HAD7 HA0/HAS HA1/HA8 HA2/HA9 HCS/HA10 HRW/HRD HDS/HWR HREQ/HTRQ HACK/HRRQ 4 2 Synchronous Serial Interface Port 0 (SSI0)2 Port C 3 SC00-SC02 SCK0 SRD0 STD0 EXTAL XTAL CLKOUT PCAP PINIT/NMI Clock/PLL Synchronous Serial Interface Port 1 (SSI1)2 Port D 3 SC10-SC12 SCK1 SRD1 STD1 MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET Interrupt/ Mode Control Dedicated General Purpose Input/ Output Port (GPIO)2 GPIO0 GPIO1 GPIO2 Port A A0-A15 D0-D23 RD WR AT MCS 16 24 External Address Bus External Data Bus External Bus Control Timers3 TIO0 TIO1 TIO2 JTAG/OnCE Port TCK TDI TDO TMS TRST DE AA0355 Note: 1. 2. 3. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or double Host Request (HR) configurations. Since each these modes is configured independently, any combination of these modes is possible. The HI08 signals can also be configured alternately as GPIO signals (PB0-PB15). The SSI0 and SSI1 signals can be configured alternatively as Port C GPIO signals (PC0-PC5) and Port D GPIO signals (PD0-PD5), respectively. TIO0-TIO2 can be configured alternatively as GPIO signals. Figure 1-1 DSP56603 Signals Identified by Functional Group 1-2 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions Power POWER Table 1-2 Power Inputs Signal Name (number of pins) VCCA (3) Signal Description Address Bus Power--VCCA is an isolated power for sections of address bus I/O drivers, and must be tied externally to all other chip power inputs, except for the VCCQL input. The user must provide adequate external decoupling capacitors. Bus Control Power--VCCC is an isolated power for the bus control I/O drivers, and must be tied to all other chip power inputs externally, except for the VCCQL input. The user must provide adequate external decoupling capacitors. Data Bus Power--VCCD is an isolated power for sections of data bus I/O drivers, and must be tied to all other chip power inputs externally, except for the VCCQL input. The user must provide adequate external decoupling capacitors. Host Power--VCCH is an isolated power for the HI08 logic, and must be tied to all other chip power inputs externally, except for the VCCQL input. The user must provide adequate external decoupling capacitors. PLL Power--VCCP is VCC dedicated for Phase Lock Loop (PLL) use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. Quiet Power High-voltage--VCCQH is an isolated power for the CPU logic, and must be tied to all other chip power inputs externally, except for the VCCQL input. The user must provide adequate external decoupling capacitors. The voltage supplied to these inputs should equal the voltage supplied to I/O power inputs VCCA, VCCC, VCCD, VCCH, and VCCS. Quiet Power Low-voltage--VCCQL is an isolated power for the CPU logic, and should not be tied to the other chip power inputs. The user must provide adequate external decoupling capacitors. SSIs, GPIO and Timers Power--VCCS is a isolated power for the SSIs, GPIO, and Timers logic, and must be tied to all other chip power inputs externally, except for the VCCQL input. The user must provide adequate external decoupling capacitors. VCCC (1) VCCD (4) VCCH (1) VCCP (1) VCCQH (3) VCCQL (4) VCCS (2) MOTOROLA DSP56603/D, Preliminary 1-3 Signal/Connection Descriptions Ground GROUND Table 1-3 Grounds Signal Name (number of pins) GNDA (4) Signal Description Address Bus Ground--GNDA is an isolated ground for sections of address bus I/O drivers, and must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Bus Control Ground--GNDC is an isolated ground for the bus control I/O drivers, and must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Data Bus Ground--GNDD is an isolated ground for sections of the data bus I/O drivers, and must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Host Ground--GNDH is an isolated ground for the HI08 I/O drivers, and must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. PLL Ground--GNDP is ground dedicated for PLL use, and should be provided with an extremely low impedance path to ground. VCCP should be bypassed to GNDP with a 0.1 F capacitor located as close as possible to the chip package. PLL Ground 1--GNDP1 is ground dedicated for PLL use, and should be provided with an extremely low impedance path to ground. Quiet Ground--GNDQ is an isolated ground for the CPU logic, and must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. SSIs, GPIO, and Timers Ground--GNDS is an isolated ground for the SSIs, GPIO, and Timers logic, and must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. GNDC (2) GNDD (4) GNDH (1) GNDP (1) GNDP1 (1) GNDQ (4) GNDS (2) 1-4 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions Clock and Phase Lock Loop CLOCK AND PHASE LOCK LOOP Table 1-4 Clock and PLL Signals Signal Name EXTAL XTAL Signal Type Input Output State During Reset Input Chipdriven Signal Description External Clock/Crystal Input--EXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock. Crystal Output--XTAL connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. PCAP Input Indeter- PLL Capacitor--PCAP is an input connecting an off-chip capacitor minate to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. CLKOUT Output Chipdriven Clock Output--CLKOUT provides an output clock synchronized to the internal core clock phase. When the PLL is enabled, the Division Factor (DF) equals one, and the Multiplication Factor (MF) is less than or equal to four, CLKOUT is also synchronized to EXTAL. When the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. PINIT/ NMI Input Input PLL Initial/Non-Maskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL Control Register 1 (PCTL1) , determining whether the PLL is enabled or disabled. After RESET deassertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered Non-Maskable Interrupt (NMI) request internally synchronized to CLKOUT. This input can tolerate 5 V. MOTOROLA DSP56603/D, Preliminary 1-5 Signal/Connection Descriptions Interrupt And Mode Control INTERRUPT AND MODE CONTROL Table 1-5 Interrupt And Mode Control Signals Signal Name RESET Signal Type Input State During Reset Input Signal Description Reset--RESET is an active low, Schmitt-trigger input. Deassertion of the RESET signal is internally synchronized to the clock out (CLKOUT). When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input, such as a capacitor charging, to reliably reset the chip. If the RESET signal is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start up synchronously and operate together. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. In addition, the value on the PINIT/NMI pin is latched to the PEN bit in the PCTL1 register. This input can tolerate 5 V. MODA/ IRQA Input Input Mode Select A/External Interrupt Request A--MODA/IRQA is an active low Schmitt-trigger input, internally synchronized to CLKOUT. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negativeedge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes latched into the Operating Mode Register (OMR) when the RESET signal is deasserted. If IRQA is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQA to exit the Wait state. If the processor is in the Stop standby state and IRQA is asserted, the processor exits the Stop state. This input can tolerate 5 V. 1-6 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions Interrupt And Mode Control Table 1-5 Interrupt And Mode Control Signals (Continued) Signal Name MODB/ IRQB Signal Type Input State During Reset Input Signal Description Mode Select B/External Interrupt Request B--MODB/IRQB is an active low Schmitt-trigger input, internally synchronized to CLKOUT. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negativeedge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes latched into the OMR when the RESET signal is deasserted. If IRQB is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQB to exit the Wait state. This input can tolerate 5 V. MODC/ IRQC Input Input Mode Select C/External Interrupt Request C--MODC/IRQCn is an active low Schmitt-trigger input, internally synchronized to CLKOUT. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negativeedge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes latched into the OMR when the RESET signal is deasserted. If IRQC is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the Wait state. This input can tolerate 5 V. MODD/ IRQD Input Input Mode Select D/External Interrupt Request D MODD/IRQD is an active low Schmitt-trigger input, internally synchronized to CLKOUT. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQD is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQD to exit the Wait state. This input can tolerate 5 V. MOTOROLA DSP56603/D, Preliminary 1-7 Signal/Connection Descriptions Expansion Port (Port A) EXPANSION PORT (PORT A) Table 1-6 Expansion Port, Port A Signals Signal Name A0-A15 Signal Type Output State During Reset Set according to chip operating mode1 Signal Description Address Bus--These active high outputs specify the address for external program memory accesses. To minimize power dissipation, A0-A15 do not change state when external memory spaces are not being accessed. D0-D23 Bi-directional Tri-stated Data Bus--These active high, bidirectional input/outputs provide the bidirectional data bus for external program memory accesses. D0-D23 are tri-stated when no external bus activity occurs. Output Pulled Memory Chip Select--This signal is an active low output, high and is asserted when an external memory access occurs. internally Pulled Read Enable--This signal is an active low output. RD is high asserted to read external memory on the data bus (D0-D23). internally Pulled Write Enable--This signal is an active low output. WR is high asserted to write external memory on the data bus (D0-D23). internally Pulled Address Tracing--This signal is an active low output. AT is high asserted (for half of a clock cycle) whenever a new address is internally driven on the address bus (A0-A15) in the Program Address Tracing mode. The new address is either a reflection of internal fetch or internal program space move instruction or an external address driven for an external access. MCS RD Output WR Output AT Output Note: 1. The A0-A15 pins are asserted according to the selected chip operating mode, as determined by the values on the MODA-MODD pins. Each mode has a different reset address. A0-A15 are latched to the value of that reset address minus 1. For example, if the reset address for a selected operating mode is $0800, the address bus is asserted to $07FF. 1-8 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions Host Interface (HI08) HOST INTERFACE (HI08) The HI08 provides a fast parallel data to 8-bit port that can be connected directly to the host bus. The HI08 supports a variety of standard buses, and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware. The direction and polarity of all pins on the HI08 is programmable. All pins also have programmable GPIO functionality. Table 1-7 Host Interface Signals Signal Name HAD0- HAD7 Signal Type Bi-directional State During Reset Tristated Signal Description Host Data Bus--When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, these signals are lines 0-7 of the Host Data bidirectional tri-state bus (HD0-HD7). Host Address and Data Bus--When the HI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 0-7 of the Host Address/Data multiplexed bidirectional tri-state bus (HAD0-HAD7). Port B 0-7--When the HI08 is configured as GPIO through the HI08 Port Control Register (HPCR), these signals are individually programmed as inputs or outputs through the HI08 Data Direction Register (HDDR). When configured as an input, this pin can tolerate 5 V. HA0/ HAS Input Tristated Host Address Input 0--When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 0 of the Host Address input bus (HA0). Host Address Strobe--When the HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the Host Address Strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable. Port B 8--When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. When configured as an input, this pin can tolerate 5 V. Bi-directional Input or Output Input Input or Output MOTOROLA DSP56603/D, Preliminary 1-9 Signal/Connection Descriptions Host Interface (HI08) Table 1-7 Host Interface Signals (Continued) Signal Name HA1/HA8 Signal Type Input State During Reset Tristated Signal Description Host Address Input 1--When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line one of the Host Address input bus (HA1). Host Address 8--When the HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line eight of the input Host Address bus (HA8). Port B 9--When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. When configured as an input, this pin can tolerate 5 V. HA2/HA9 Input Tristated Host Address Input 2--When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line two of the Host Address input bus (HA2). Host Address 9--When the HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line nine of the input Host Address bus (HA9). Port B 10--When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. When configured as an input, this pin can tolerate 5 V. Input Input or Output Input Input or Output 1-10 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions Host Interface (HI08) Table 1-7 Host Interface Signals (Continued) Signal Name HRW/HRD Signal Type Input State During Reset Tristated Signal Description Host Read/Write--When the HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the Read/Write input (HRW). Host Read Data--When the HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the Read Data strobe Schmitt-trigger input (HRD). The polarity of the data strobe is programmable. Port B 11--When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. When configured as an input, this pin can tolerate 5 V. HDS/HWR Input Tristated Host Data Strobe--When the HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the Host Data Strobe Schmitttrigger input (HDS). The polarity of the data strobe is programmable. Host Write Enable--When the HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the Write Data Strobe Schmitt-trigger input (HWR). The polarity of the data strobe is programmable. Port B 12--When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. When configured as an input, this pin can tolerate 5 V. Input Input or Output Input Input or Output MOTOROLA DSP56603/D, Preliminary 1-11 Signal/Connection Descriptions Host Interface (HI08) Table 1-7 Host Interface Signals (Continued) Signal Name HCS/HA10 Signal Type Input State During Reset Tristated Signal Description Host Chip Select--When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is the Host Chip Select input (HCS). The polarity of the chip select is programmable. Host Address 10--When the HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the input Host Address bus (HA10). Port B 13--When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. When configured as an input, this pin can tolerate 5 V. HREQ/ HTRQ Output Tristated Host Request--When the HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the Host Request output (HREQ). The polarity of the host request is programmable. The host request can be programmed as a driven or open-drain output. Transmit Host Request--When the HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the Transmit Host Request output (HTRQ). The polarity of the host request is programmable. The host request can be programmed as a driven or open-drain output. Port B 14--When the HI08 is programmed to interface a multiplexed host bus and the signal is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. When configured as an input, this pin can tolerate 5 V. Input Input or Output Output Input or Output 1-12 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions Host Interface (HI08) Table 1-7 Host Interface Signals (Continued) Signal Name HACK/ HRRQ Signal Type Input State During Reset Tristated Signal Description Host Acknowledge --When the HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the Host Acknowledge Schmitt-trigger input (HACK). The polarity of the host acknowledge is programmable. Receive Host Request--When the HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the Receive Host Request output (HRRQ). The polarity of the host request is programmable. The host request can be programmed as a driven or open-drain output. Port B 15--When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. When configured as an input, this pin can tolerate 5 V. Output Input or Output MOTOROLA DSP56603/D, Preliminary 1-13 Signal/Connection Descriptions Synchronous Serial Interface 0 (SSI0) SYNCHRONOUS SERIAL INTERFACE 0 (SSI0) Two identical Synchronous Serial Interfaces (SSI0 and SSI1) provide a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, or microprocessors. When either SSI port is disabled, it can be used for General Purpose I/O (GPIO). Table 1-8 Synchronous Serial Interface 0 (SSI0) Signal Name SC00 Signal Type Input or Output State During Reset Tristated Signal Description Serial Control Signal 0--The function of SC00 is determined by the selection of either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is used for or for Serial I/O Flag 0. Port C 0--When configured as PC0, signal direction is controlled through the SSI0 Port Direction Control Register (PRRC). The signal can be configured as SSI signal SC00 through the SSI0 Port Control Register (PCRC). When configured as an input, this pin can tolerate 5 V. SC01 Input or Output Tristated Serial Control Signal 1--The function of SC00 is determined by the selection of either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is used for Serial I/O Flag 1. Port C 1--When configured as PC1, signal direction is controlled through the PRRC. The signal can be configured as an SSI signal SC01 through the PCRC. When configured as an input, this pin can tolerate 5 V. Input or Output Input or Output 1-14 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions Synchronous Serial Interface 0 (SSI0) Table 1-8 Synchronous Serial Interface 0 (SSI0) (Continued) Signal Name SC02 Signal Type Input or Output State During Reset Tristated Signal Description Serial Control Signal 2--SC02 is the frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port C 2--When configured as PC2, signal direction is controlled through the PRRC. The signal can be configured as an SSI signal SC02 through the PCRC. When configured as an input, this pin can tolerate 5 V. SCK0 Input or Output Tristated Serial Clock--SCK0 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the SSI interface. The SCK0 is a clock input or output used by both the transmitter and receiver in Synchronous modes, or by the transmitter in Asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (i.e., the system clock frequency must be at least three times the external SSI clock frequency). The SSI needs at least three DSP phases inside each half of the serial clock. Input or Output Port C 3--When configured as PC3, signal direction is controlled through the PRRC. The signal can be configured as an SSI signal SCK0 through the PCRC. When configured as an input, this pin can tolerate 5 V. SRD0 Input Tristated Serial Receive Data--SRD0 receives serial data and transfers the data to the SSI Receive Shift Register. Port C 4--When configured as PC4, signal direction is controlled through the PRRC. The signal can be configured as an SSI signal SRD0 through the PCRC. When configured as an input, this pin can tolerate 5 V. Input or Output Input or Output MOTOROLA DSP56603/D, Preliminary 1-15 Signal/Connection Descriptions Synchronous Serial Interface 0 (SSI0) Table 1-8 Synchronous Serial Interface 0 (SSI0) (Continued) Signal Name STD0 Signal Type Output State During Reset Tristated Signal Description Serial Transmit Data--STD0 is used for transmitting data from the SSI Transmit Shift Register. Port C 5--When configured as PC5, signal direction is controlled through the PRRC. The signal can be configured as an SSI signal STD0 through the PCRC. When configured as an input, this pin can tolerate 5 V. Input or Output 1-16 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions Synchronous Serial Interface 1 (SSI1) SYNCHRONOUS SERIAL INTERFACE 1 (SSI1) Table 1-9 Synchronous Serial Interface 1 (SSI1) Signal Name SC10 Signal Type Input or Output State during Reset Tristated Signal Description Serial Control Signal 0--The function of SC10 is determined by the selection of either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is used for or for Serial I/O Flag 0. Port D 0--When configured as PD0, signal direction is controlled through the SSI1 Port Direction Control Register (PRRD). The signal can be configured as SSI signal SC10 through the SSI1 Port Control Register (PCRD). When configured as an input, this pin can tolerate 5 V. SC11 Input or Output Tristated Serial Control Signal 1--The function of SC11 is determined by the selection of either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is used for Serial I/O Flag 1. Port D 1--When configured as PD1, signal direction is controlled through the PRRD. The signal can be configured as an SSI signal SC11 through the PCRD. When configured as an input, this pin can tolerate 5 V. SC12 Input or Output Tristated Serial Control Signal 2--SC12 is used for frame sync I/O. SC12 is the frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port D 2--When configured as PD2, signal direction is controlled through the PRRD. The signal can be configured as an SSI signal SC12 through the PCRD. When configured as an input, this pin can tolerate 5 V. Input or Output Input or Output Input or Output MOTOROLA DSP56603/D, Preliminary 1-17 Signal/Connection Descriptions Synchronous Serial Interface 1 (SSI1) Table 1-9 Synchronous Serial Interface 1 (SSI1) (Continued) Signal Name SCK1 Signal Type Input or Output State during Reset Tristated Signal Description Serial Clock--SCK1 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the SSI interface. The SCK1 is a clock input or output used by both the transmitter and receiver in Synchronous modes, or by the transmitter in Asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (i.e., the system clock frequency must be at least three times the external SSI clock frequency). The SSI needs at least three DSP phases inside each half of the serial clock. Input or Output Port D 3--When configured as PD3, signal direction is controlled through the PRRD. The signal can be configured as an SSI signal SCK1 through the PCRD. When configured as an input, this pin can tolerate 5 V. SRD1 Input Tristated Serial Receive Data--SRD1 receives serial data and transfers the data to the SSI Receive Shift Register. Port D 4--When configured as PD4, signal direction is controlled through the PRRD. The signal can be configured as an SSI signal SRD1 through the PCRD. When configured as an input, this pin can tolerate 5 V. STD1 Output Tristated Serial Transmit Data--STD1 is used for transmitting data from the SSI Transmit Shift Register. Port D 5--When configured as PD5, signal direction is controlled through the PRRD. The signal can be configured as an SSI signal STD1 through the PCRD. When configured as an input, this pin can tolerate 5 V. Input or Output Input or Output 1-18 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions General Purpose I/O, GPIO GENERAL PURPOSE I/O, GPIO Three dedicated General Purpose Input/Output (GPIO) signals are provided on the DSP56603. Each is reconfigurable as input, output, or tri-state. These signals are exclusively defined as GPIO, and do not offer additional functionality. Table 1-10 General Purpose I/O (GPIO) Signal Name GPIO0 Signal Type Input or Output State during Reset Input Signal Description General Purpose I/O --When a GPIO signal is used as input, the logic state is reflected to an internal register and can be read by the software. When a GPIO signal is used as output, the logic state is controlled by the software. This input can tolerate 5 V. GPIO1 Input or Output Input General Purpose I/O --When a GPIO signal is used as input, the logic state is reflected to an internal register and can be read by the software. When a GPIO signal is used as output, the logic state is controlled by the software. This input can tolerate 5 V. GPIO2 Input or Output Input General Purpose I/O --When a GPIO signal is used as input, the logic state is reflected to an internal register and can be read by the software. When a GPIO signal is used as output, the logic state is controlled by the software. This input can tolerate 5 V. MOTOROLA DSP56603/D, Preliminary 1-19 Signal/Connection Descriptions Triple Timer TRIPLE TIMER Three identical and independent timers are implemented. The three timers can use internal or external clocking and can interrupt the DSP after a specified number of events (clocks), or can signal an external device after counting a specific number of internal events. When a timer port is disabled, it can be used for General Purpose I/O (GPIO). Table 1-11 Triple Timer Signals Signal Name TIO0 Signal Type Input or Output State during Reset GPIO Input Signal Description Timer 0 Schmitt-Trigger Input/Output --When TIO0 is used as an input, the timer module functions as an external event counter or measures external pulse width or signal period. When TIO0 is used as an output, the timer module functions as a timer and TIO0 provides the timer pulse. When the TIO0 is not used by the timer module, it can be used for Input or Output GPIO. When configured as an input, this pin can tolerate 5 V. TIO1 Input or Output GPIO Input Timer 1 Schmitt-Trigger Input/Output --When TIO1 is used as an input, the timer module functions as an external event counter or measures external pulse width or signal period. When TIO1 is used as an output, the timer module functions as a timer and TIO1 provides the timer pulse. When TIO1 is not used by the timer module, it can be used for Input or Output GPIO. When configured as an input, this pin can tolerate 5 V. TIO2 Input or Output GPIO Input Timer 2 Schmitt-Trigger Input/Output --When TIO2 is used as an input, the timer module functions as an external event counter or measures external pulse width or signal period. When TIO2 is used as an output, the timer module functions as a timer and TIO2 provides the timer pulse. When TIO2 is not used by the timer module, it can be used for Input or Output GPIO. When configured as an input, this pin can tolerate 5 V. 1-20 DSP56603/D, Preliminary MOTOROLA Signal/Connection Descriptions JTAG/OnCE Interface JTAG/OnCE INTERFACE Table 1-12 JTAG/On-Chip Emulation (OnCE) Interface Signals Signal Name TCK Signal Type Input State During Reset Input Signal Description Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. The TCK pin can be tri-stated. This input can tolerate 5 V. TDI Input Input Test Data Input-- TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of the TCK signal and has an internal pull-up resistor. This input can tolerate 5 V. TDO Output Tri-state Test Data Output-- TDO is a test data serial output signal used for test instructions and data. TDO is tri-stateable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of the TCK signal. Input Test Mode Select-- TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of the TCK signal and has an internal pull-up resistor. This input can tolerate 5 V. TRST Input Input Test Reset--TRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. TRST must be asserted during the power up sequence. This input can tolerate 5 V. DE Bi-directional Input Debug Event--DE is an open-drain bidirectional active-low signal providing, as an input, a means of entering the Debug mode of operation from an external command controller, and as an output, a means of acknowledging that the chip has entered the Debug mode. The DE has an internal pull-up resistor. When this pin is an input, it can tolerate 5 V. TMS Input MOTOROLA DSP56603/D, Preliminary 1-21 Signal/Connection Descriptions JTAG/OnCE Interface 1-22 DSP56603/D, Preliminary MOTOROLA SECTION 2 SPECIFICATIONS GENERAL CHARACTERISTICS The DSP56603 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL)-compatible inputs and outputs. Functional operating conditions are given in Table 2-4 on page 2-3. Absolute maximum ratings given in Table 2-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The DSP56603 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. Table 2-1 Absolute Maximum Ratings (GND = 0 V) Rating Supply Voltage All Input Voltages Excluding "5 Volt Tolerant" Inputs All "5 Volt Tolerant" Inputs Voltages1 Current Drain per Pin Excluding VCC and GND Operating Temperature Range Storage Temperature Note: 1. Symbol VCC VIN VIN5 I Value -0.3 to +4 GND - 0.3 to VCC + 0.3 GND - 0.3 to VCC + 3.95 10 Unit V V V mA C C TA Tstg -40 to 85 -55 to +150 "5 Volt Tolerant" inputs are inputs that tolerate 5 V. All "5 Volt Tolerant" input voltages cannot be more than 3.95 V greater than supply voltage. This restriction applies to power-on, as well as to normal operation. MOTOROLA DSP56603/D, Preliminary 2-1 Specifications General Characteristics CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either or VCC or GND). Table 2-2 Recommended Operating Conditions Rating Supply Voltage Ambient Temperature Symbol VCC TA Value 2.7 to 3.3 -40 to +85 Unit V C Table 2-3 Package Thermal Characteristics 144-pin TQFP Thermal Resistance1 Symbol Junction-to-ambient thermal resistance2 Junction-to-case thermal resistance3 Thermal characterization parameter Notes: 1. 2. 3. 4. Value 49.3 8.2 5.5 Units C/W C/W C/W RJA or JA RJC or JC JT 5. 6. See discussion under Heat Dissipation on page 4-1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI G38-87 in natural convection. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. Thermal Characterization Parameter, JT, is defined in EIA/JESD 51-2. It is a measure of the difference in temperature between the junction and a thermocouple on top of the package normalized by the power dissipation. SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Road, Mountain View, CA 94043, (415) 964-5111. MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at (800) 854-7179 or (303) 397-7956. 2-2 DSP56603/D, Preliminary MOTOROLA Specifications DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) Table 2-4 DC Electrical Characteristics for the DSP56603 Characteristics Supply Voltage for VCCA, VCCC, VCCD, VCCH, VCCP, VCCQH, VCCQL, and VCCS1 Input High Voltage * D0-D23 * MOD/IRQ2, RESET, PINIT/NMI, and all JTAG/HI08/SSI/Timer/GPIO pins * EXTAL Input Low Voltage * D0-D23, MOD/IRQ2, RESET, PINIT/NMI * all JTAG/HI08/SSI/Timer/GPIO pins * EXTAL Input Leakage Current High-Impedance (Off State) Input Current (2.4 V/0.4 V) Output High Voltage (IOH = -0.4 mA) Output Low Voltage (IOL = 3.0 mA, Open Drain Pins IOL = 6.7 mA) Internal Supply Current at 60 MHz * in Normal Mode3, 6 * in Wait Mode4, 6 * in Stop Mode5, 6 PLL Supply Current in Stop Mode (PLL on)6 Input Capacitance6 Notes: 1. 2. 3. Symbol VCC Min 2.7 Typ 3.0 Max 3.3 Unit V VIH VIHP VIHX VIL VILP VILX IIN ITSI VOH VOL 2.0 2.0 VCC - 0.4 -0.3 -0.3 -0.3 -10.0 -10.0 2.4 -- -- -- -- -- -- -- -- -- -- -- VCC 5.75 VCC 0.8 0.8 0.4 10.0 10.0 -- 0.4 V V V V V V A A V V ICCI ICCW ICCS IPLL CIN -- -- -- -- -- 57 4.6 50 3.5 -- -- -- -- -- 10 mA mA A mA pF 4. 5. 6. Throughout the data sheet, assume that VCCA, VCCC, VCCD, VCCH, VCCP, VCCQH, VCCQL, and VCCS power pins have the same voltage level. This specification applies to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins. Power Consumption Considerations on page 4-5 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see Appendix A). The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 2.7 V at TJ = 100C. The actual current consumption varies with the operating conditions and the program being executed. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). In order to obtain these results, all inputs that are not disconnected at Stop mode must be terminated. These values are periodically sampled and not 100% tested. MOTOROLA DSP56603/D, Preliminary 2-3 Specifications AC Electrical Characteristics AC ELECTRICAL CHARACTERISTICS The timing specifications in AC Electrical Characteristics are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels set forth in DC Electrical Characteristics. AC timing specifications referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. Timings specified relative to a CLKOUT edge are measured with respect to the 50% point of the applicable CLKOUT transition. All other DSP56603 output timing specifications are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively. Note: Unless specifically noted otherwise, all references to CLKOUT edges assume that the PLL is enabled. All timings except those that specifically relate to the EXTAL input are guaranteed by test with the PLL enabled. AC Electrical Characteristics--Internal Clock Operation (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) For each occurrence of TH, TL, TC, or ICYC, substitute the numbers given in Table 2-5. (The terms Ef, ETH, ETL, and ETC are described in Table 2-6.) Table 2-5 Internal Clocks Characteristics Internal Operation Frequency With PLL Enabled Internal Operation Frequency With PLL Disabled Internal Clock High Period * PLL disabled * PLL enabled and MF 4 Symbol f f TH Expression (Ef x MF1)/(PDF2 x DF3) Ef/2 ETC (Min) 0.49 x ETC x PDF x DF/MF (Max) 0.51 x ETC x PDF x DF/MF (Min) 0.47 x ETC x PDF x DF/MF (Max) 0.53 x ETC x PDF x DF/MF TL ETC (Min) 0.49 x ETC x PDF x DF/MF (Max) 0.51 x ETC x PDF x DF/MF (Min) 0.47 x ETC x PDF x DF/MF (Max) 0.53 x ETC x PDF x DF/MF * PLL enabled and MF > 4 Internal Clock Low Period * PLL disabled * PLL enabled and MF 4 * PLL enabled and MF > 4 2-4 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics Table 2-5 Internal Clocks (Continued) Characteristics Internal Clock Cycle Time With PLL Enabled Internal Clock Cycle Time With PLL Disabled Instruction Cycle Time Notes: 1. 2. 3. MF represents the PLL Multiplication Factor. PDF represents the PLL Predivision Factor. DF represents the PLL Division Factor. Symbol TC TC ICYC Expression ETC x PDF x DF/MF 2 x ETC TC AC Electrical Characteristics--External Clock Operation (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) The DSP56603 system clock can be derived from the on-chip crystal oscillator, or it can be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically not connected to the board or socket (see Figure 2-1 on page 2-6). The rise and fall time of this external clock should be 3 ns maximum. Table 2-6 Clock Operation Num 1 2 Characteristics Frequency of EXTAL (EXTAL Pin Frequency) Clock Input High1, 2 * PLL disabled (46.7-53.3% duty cycle) * PLL enabled (42.5-57.5% duty cycle, at 60 MHz) Clock Input Low1, 2 * PLL disabled (46.7-53.3% duty cycle) * PLL enabled (42.5-57.5% duty cycle) Clock Cycle Time 2 * PLL disabled * PLL enabled CLKOUT Change from EXTAL Fall, PLL disabled CLKOUT from EXTAL with PLL enabled (MF = PDF x DF, MF 4, Ef > 15 MHz)4 Instruction Cycle Time = ICYC = TC 1, 3 * PLL disabled * PLL enabled Symbol Ef ETH Min 0 7.8 7.1 7.8 7.1 16.7 16.7 4.3 0 Max 60.0 157.0 s 157.0 s 273.1 s 11.0 1.8 Unit MHz ns 3 ETL ns 4 ETC ns ns ns 5 6 7 -- -- ICYC 33.3 16.7 8.53 s ns MOTOROLA DSP56603/D, Preliminary 2-5 Specifications AC Electrical Characteristics Table 2-6 Clock Operation (Continued) Num Notes: 1. 2. 3. 4. Characteristics Symbol Min Max Unit External Clock Input High, External Clock Input Low, and CLKOUT are measured at 50% of the signal transition. The maximum value for PLL enabled is given for minimum VCO and maximum MF. The maximum value for PLL enabled is given for minimum VCO and maximum DF. These timings are periodically sampled and not 100% tested. EXTAL R1 XTAL R2 EXTAL R XTAL C XTAL1 C C XTAL1 C Fundamental Frequency Fork Crystal Oscillator Suggested Component Values: fOSC = 32.768 kHz R1 = 3.9 M 10% R2 = 200 k 10% C = 22 pF 20% Calculations were done for a 32.768 kHz crystal with the following parameters: a load capacitance (CL) of 12.5 pF, a shunt capacitance (C0) of 1.8 pF, a series resistance of 40 k, and drive level of 1 W. Fundamental Frequency Crystal Oscillator Suggested Component Values: fOSC = 4 MHz R = 680 k 10% C = 56 pF 20% fOSC = 20 MHz R = 680 k 10% C = 22 pF 20% Calculations were done for a 4/20 MHz crystal with the following parameters: a load capacitance (CL)of 30/20 pF, a shunt capacitance (C0) of 7/6 pF, a series resistance of 100/20 , and drive level of 2 mW. AA0458 Figure 2-1 Crystal Oscillator Circuits 2-6 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics VIHC EXTAL VILC ETH 2 ETL 4 5 CLKOUT With PLL Disabled 7 CLKOUT With PLL Enabled 6 Note: The midpoint is 0.5 (VIHC + VILC). 7 AA0367 Midpoint 3 ETC 5 Figure 2-2 External Clock Timing AC Electrical Characteristics--Phase Lock Loop (PLL) Characteristics (VCC = 3.0 V 0.3 V; TA = -40 to 85 C, CL = 50 pF + 2 TTL Loads) Table 2-7 Phase Lock Loop Characteristics Characteristics VCO frequency when PLL enabled 1 PLL external capacitor (PCAP pin to VCCP) * MF 4 * MF > 4 Notes: 1. Expression MF x Ef x 2 / PDF Cpcap 2 Min 30 Max 120 Unit MHz pF MF x 425 - 125 MF x 590 - 175 MF x 520 MF x 920 2. The VCO output is further divided by 2 when PLL is enabled. If the Division Factor (DF) is 1, the operating frequency is VCO . -----------2 Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP). (The recommended value for Cpcap is (500 x MF - 150) pF for MF 4 and (690 x MF) pF for MF > 4.) MOTOROLA DSP56603/D, Preliminary 2-7 Specifications AC Electrical Characteristics AC Electrical Characteristics--Reset, Stop, Mode Select, and Interrupt Timing (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) WS = Number of Wait States (measured in clock cycles, number of TC) Table 2-8 Reset Timing 60 MHz Num 8 9 Characteristics Delay from RESET Assertion to All Pins at Reset Value1 Expression Min Max 20.0 + TC -- 833.3 16.72 1.25 1.25 41.7 41.7 333.34 -- -- -- -- -- -- ns ns s ms ms ns ns Unit Required RESET Duration 2, 3 * Power on, external clock generator, PLL disabled 50 x ETC * Power on, external clock generator, PLL enabled 1000 x ETC * Power on, internal oscillator 75000 x ETC * During Stop, XTAL disabled 75000 x ETC * During Stop, XTAL enabled 2.5 x TC * During normal operation 2.5 x TC Delay from Asynchronous RESET Deassertion to First External Address Output (Internal Reset Deassertion)4 * Minimum * Maximum Synchronous Reset Setup Time from RESET Deassertion to first CLKOUT transition Synchronous Reset Deassertion, Delay Time from the first CLKOUT transition to the First External Address Output * Minimum * Maximum 1. 2. 10 3.25 x TC + 2.2 56.4 -- 20.25TC + 12.1 -- 349.6 TC 9.0 16.7 ns ns ns 11 12 3.25 x TC + 1.1 55.3 -- 20.25TC + 5.5 -- 343.0 ns ns Notes: 3. 4. These timings are periodically sampled and not 100% tested. For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When VCC is powered up and the "Required RESET Duration" conditions as specified above are not yet met, the device circuitry is in an uninitialized state that may result in significant power consumption. To minimize power consumption, the DSP56603 should be initialized as soon as possible to limit the duration of the uninitialized state. This specification is valid if the PLL does not lose lock. 2-8 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics VIH RESET 9 8 All Pins 10 A0-A15 First Fetch AA0367 Figure 2-3 Reset Timing CLKOUT 11 RESET 12 A0-A15 AA0368 Figure 2-4 Synchronous Reset Timing Table 2-9 Mode Select and Interrupt Timings 60 MHz Num 13 14 15 16 17 Characteristics Mode Select Setup Time Mode Select Hold Time Minimum Edge-Triggered Interrupt Request Assertion Width Minimum Edge-Triggered Interrupt Request Deassertion Width Delay from IRQ or NMI Assertion to External Memory Access Address Out Valid * Caused by first interrupt instruction fetch * Caused by first interrupt instruction execution Expression Min -- -- -- -- 30.0 0.0 10.0 10.0 Max -- -- -- -- ns ns ns ns Unit 4.25 x TC + 2.2 7.25 x TC + 2.2 73.0 123.0 -- -- ns ns MOTOROLA DSP56603/D, Preliminary 2-9 Specifications AC Electrical Characteristics Table 2-9 Mode Select and Interrupt Timings (Continued) 60 MHz Num 18 Characteristics Delay from IRQA, IRQB, IRQC, IRQD, NMI Assertion to General Purpose Transfer Output Valid caused by First Interrupt Instruction Execution Delay from Address Output Valid caused by First Interrupt Instruction Execute to Interrupt Request Deassertion for Level Sensitive Fast Interrupts1 Delay from RD Assertion to Interrupt Request Deassertion for Level Sensitive Fast Interrupts1 Expression Min 10 x TC + 5.5 172.2 Max -- ns Unit 19 3.75 x TC + WS x TC - 15.4 3.25 x TC + WS x TC - 15.4 -- 63.8 ns 20 21 -- 55.4 ns Delay from WR Assertion to Interrupt Request Deassertion for Level Sensitive Fast Interrupts1 * SRAM WS = 1 (3.5 + WS) x TC - 15.4 * SRAM WS = 2, 3 (3.0 + WS) x TC - 15.4 * SRAM WS 4 (2.5 + WS) x TC - 15.4 Synchronous Interrupt Setup Time from IRQA, IRQB, IRQC, IRQD, NMI Assertion to the Second CLKOUT transition Synchronous Interrupt Delay Time from CLKOUT's Second Transition to the First External Address Output Valid caused by the First Instruction Fetch after coming out of Wait * Minimum * Maximum Duration for IRQA Assertion to recover from Stop TC -- -- -- 9.0 59.6 51.3 26.3 16.7 ns ns ns ns 22 23 9.25 x TC + 1.1 24.75 x TC + 5.5 -- 155.3 -- 9.0 -- 418.0 -- ns ns ns 24 25 Delay from IRQA assertion To Fetch of First Instruction (when exiting Stop) 2, 3 * PLL not active during Stop and Stop PLC x ETC x PDF + 2.2 Delay enabled (PCTL1 Bit 6 = 0, OMR (128K - PLC/2) x TC Bit 6 = 0) * PLL not active during Stop, Stop Delay PLC x ETC x PDF + 388.3 ns not enabled (23.75 0.5) x TC (PCTL1 Bit 6 = 0, OMR Bit 6 = 1) * PLL active during Stop, no Stop Delay PLC x ETC 129.2 (PCTL1 Bit 6 = 1) (8.25 0.5) x TC 22.6 ms 20.4 ms 145.8 ns 2-10 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics Table 2-9 Mode Select and Interrupt Timings (Continued) 60 MHz Num 26 Characteristics Expression Min Duration of Level-Sensitive IRQA Assertion to Ensure Interrupt Service (when exiting Stop) 2,3 * PLL not active during Stop, Stop Delay PLC x ETC x PDF + enabled (128K - PLC/2) x TC (PCTL1 Bit 6 = 0, OMR Bit 6 = 0) * PLL not active during Stop, Stop Delay PLC x ETC x PDF + not enabled (20.5 0.5) x TC (PCTL1 Bit 6 = 0, OMR Bit 6 = 1) 5.5 x TC * PLL active during Stop, no Stop Delay (PCTL1 Bit 6 = 1) Interrupt requests rate * HI08, SSI, Timer * IRQ (edge trigger) * IRQ (level trigger) 1. Unit Max 22.6 -- ns 20.4 -- ns 91.7 -- ns 27 12TC 8TC 12TC -- -- -- 200.4 133.6 200.4 ns Notes: 2. 3. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, then timings 14 through 16 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using level-sensitive mode. This timing depends on several settings: * For PLL disabled, using internal oscillator (PLL Control Register (PCTL)1 Bit 4 = 0) and oscillator disabled during Stop (PCTL1 Bit 5 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) provides the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case. * For PLL disabled, using internal oscillator (PCTL1 Bit 4 = 0) and oscillator enabled during Stop (PCTL1 Bit 5 = 1), no stabilization delay is required and recovery time is minimal (OMR Bit 6 setting is ignored). * For PLL disabled, using external clock (PCTL1 Bit 4 = 1), no stabilization delay is required and recovery time is defined by the PCTL1 Bit 6 and OMR Bit 6 settings. * For PLL disabled, using external clock (PCTL1 Bit 4 = 1), no stabilization delay is required and recovery time is defined by the PCTL1 Bit 6 and OMR Bit 6 settings. * For PLL enabled, if PCTL1 Bit 6 is 0, the PLL is shut down during Stop. Recovering from Stop requires the PLL to re-lock. The PLL lock procedure duration, PLC (PLL Lock Cycles), may be in the range of 0 to 300 cycles. This procedure occurs in parallel to the Stop Delay counter, and Stop recovery ends when the last of these two events occurs (the Stop Delay counter completes its count, or the PLL lock procedure completes). * PLC value for PLL disabled is 0. * Maximum value for ETC is 4096 (maximum multiplication factor) divided by the desired internal frequency (i.e., for 60 MHz it is 4096/60 MHz = 68.26 s). During the stabilization period, TC, TH, and TL will not be constant. Their width may vary, so timing may vary as well. These timings are periodically sampled and not 100% tested. MOTOROLA DSP56603/D, Preliminary 2-11 Specifications AC Electrical Characteristics A0-A15 First Interrupt Instruction Execution/Fetch RD 20 WR 21 IRQA, IRQB, IRQC, IRQD, NMI 17 19 a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O AA0369 Figure 2-5 External Level--Sensitive Fast Interrupt Timing IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI 16 AA0370 Figure 2-6 External Interrupt Timing (Negative Edge-Triggered) 2-12 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics CLKOUT T0, T2 22 T1, T3 IRQA IRQB, IRQC, IRQD, NMI 23 A0-A15 AA0371 Figure 2-7 Synchronous Interrupt from Wait Timing VIH RESET 13 VIH MODA, MODB, MODC, MODD VIL 14 VIH VIL AA0372 Figure 2-8 Operating Mode Select Timing 24 IRQA 25 A0-A15, MCS First Instruction Fetch AA0373 Figure 2-9 Recovery from Stop Using IRQA 26 IRQA 25 A0-A15, MCS First IRQA Interrupt Instruction Fetch AA0374 Figure 2-10 Recovery from Stop Using IRQA Interrupt Service MOTOROLA DSP56603/D, Preliminary 2-13 Specifications AC Electrical Characteristics AC Electrical Characteristics--Port A (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) Table 2-10 SRAM Read and Write Access 60 MHz Num Characteristics Symbol Expression Min 100 Address Valid and MCS Assertion Pulse Width * 1 WS 3 * 4 WS 7 * WS 8 Address Valid and MCS Assertion to WR Assertion * WS = 1 * 2 WS 3 * WS 4 WR Assertion Pulse Width * WS = 1 * 2 WS 3 * WS 4 WR Deassertion to Address Invalid and MCS Deassertion * 1 WS 3 * 4 WS 7 * WS 8 Address and MCS Valid to Input Data Valid, WS 1 RD Assertion to Input Data Valid, WS 1 RD Deassertion to Data Invalid (Data Hold Time) Address Valid to WR Deassertion, WS 1 Data Valid to WR Deassertion (Data setup time), WS 1 tRC, tWC (WS + 1) x TC - 4.4 (WS + 2) x TC - 4.4 (WS + 3) x TC - 4.4 tAS 0.25 x TC - 3.7 0.75 x TC - 4.4 1.25 x TC - 4.4 tWP 1.5 x TC - 5.7 WS x TC - 4.4 (WS - 0.5) x TC - 4.4 0.5 8.1 16.4 19.3 28.9 53.9 -- -- -- -- -- -- ns 28.9 95.6 178.9 -- -- -- ns Max Unit 101 102 ns 103 tWR 0.25 x TC - 3.8 1.25 x TC - 4.4 2.25 x TC - 4.4 tAA, tAC tOE tOHZ tAW tDS (tDW) (WS + 0.75) x TC - 8.5 (WS + 0.5) x TC - 8.5 -- (WS + 0.75) x TC - 4.4 (WS - 0.25) x TC - 3.9 0.4 16.4 33.1 -- -- 0.0 24.8 8.6 -- -- -- 20.7 16.5 -- -- -- ns 104 105 106 107 108 ns ns ns ns ns 2-14 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics Table 2-10 SRAM Read and Write Access (Continued) 60 MHz Num Characteristics Symbol Expression Min 109 Data Hold Time from WR Deassertion * 1 WS 3 * 4 WS 7 * WS 8 WR Assertion to Data Active * WS = 1 * 2 WS 3 * WS 4 WR Deassertion to Data High Impedance * 1 WS 3 * 4 WS 7 * WS 8 Previous RD Deassertion to Data Active (Write) * 1 WS 3 * 4 WS 7 * WS 8 RD Deassertion Time * 1 WS 3 * 4 WS 7 * WS 8 WR Deassertion Time * WS = 1 * 2 WS 3 * 4 WS 7 * WS 8 Address Valid to RD Assertion RD Assertion Pulse Width RD Deassertion to Address Invalid * 1 WS 3 * 4 WS 7 * WS 8 tDH 0.25 x TC - 3.8 1.25 x TC - 3.8 2.25 x TC - 3.8 -- 0.75 x TC - 3.7 0.25 x TC - 3.7 -0.25 x TC - 3.7 0.4 17.0 33.7 8.8 0.5 -7.9 -- -- -- -- -- -- ns Max Unit 110 ns 111 -- 0.25 x TC + 0.6 1.25 x TC + 0.6 2.25 x TC + 0.6 -- 1.25 x TC - 4.4 2.25 x TC - 4.4 3.25 x TC - 4.4 -- 0.75 x TC - 4.4 1.75 x TC - 4.4 2.75 x TC - 4.4 0.5 x TC - 3.1 TC - 3.1 2.5 x TC - 3.1 3.5 x TC - 3.1 0.5 x TC - 4.0 (WS + 0.25) x TC - 3.8 16.4 33.1 49.8 8.1 24.8 41.4 5.2 13.6 38.6 55.2 4.3 17.0 -- -- -- -- -- -- -- -- -- -- -- ns -- -- -- 4.8 21.4 38.1 ns 112 113 ns 114 -- ns 115 116 117 -- -- -- ns ns 0.25 x TC - 3.0 1.25 x TC - 3.0 2.25 x TC - 3.0 1.2 17.8 34.5 -- -- -- ns MOTOROLA DSP56603/D, Preliminary 2-15 Specifications AC Electrical Characteristics Table 2-10 SRAM Read and Write Access (Continued) 60 MHz Num Characteristics Symbol Expression Min Notes: 1. 2. 3. Unit Max WS refers to the number of Wait States, as specified in the BCR. The asynchronous delays specified in the expressions are valid for DSP56603-60. The Address Trace (AT) pin is also active on accesses to internal program memory if the Address Trace Enable (ATE) bit (Bit 15) of the OMR is set. In this case, the MCS, RD, and WR signals are deasserted and the data bus is tri-stated while the address bus is driven with the address of the internal access. 100 A0-A15, MCS 113 RD 115 WR 104 D0-D23 250 AT AA0375 116 117 105 106 Data In 251 Figure 2-11 SRAM Read Access 2-16 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics 100 A0-A15, MCS 107 101 WR 114 RD 108 110 112 D0-D23 250 AT AA0376 102 103 111 109 Data In 251 Figure 2-12 SRAM Write Access Table 2-11 External Bus Synchronous Timings (SRAM Access) 60 MHz Num 198 199 202 203 204 205 206 207 Characteristics CLKOUT Low to Address Valid and MCS Assertion CLKOUT Low to Address Invalid and MCS Deassertion CLKOUT Low to Data Out Active5 CLKOUT Low to Data Out Valid CLKOUT Low to Data Out Invalid CLKOUT Low to Data Out High Z5 Data in valid to CLKOUT Low (Setup) CLKOUT Low to Data In Invalid (Hold) Expression Min 0.25 x TC + 5.5 0.25 x TC 0.25 x TC 0.25 x TC + 5.5 0.25 x TC 0.25 x TC + 1.1 -- -- -- 4.2 4.2 -- 4.2 -- 3.0 0.0 Max 9.7 -- -- 9.7 -- 5.3 -- -- ns ns ns ns ns ns ns ns Unit MOTOROLA DSP56603/D, Preliminary 2-17 Specifications AC Electrical Characteristics Table 2-11 External Bus Synchronous Timings (SRAM Access) (Continued) 60 MHz Num 208 Characteristics CLKOUT Low to RD Assertion * Minimum * Maximum CLKOUT Low to RD Deassertion CLKOUT Low to WR Assertion3 * WS = 1 * 2 WS 3 * WS 4 CLKOUT Low to WR Deassertion 1. 2. 3. 4. 5. Expression Min 0.5 x TC + 1.1 0.5 x TC + 5.5 -- 0.5 x TC + 6.2 -- 0.5 x TC + 6.2 -- 9.4 -- 0.0 10.1 1.8 10.1 0.0 Max -- 13.8 5.5 14.5 6.2 14.5 4.9 Unit ns ns ns ns 209 210 211 Notes: ns WS is the number of Wait States specified in the BCR. The asynchronous delays specified in the expressions are valid for DSP56603-60. If WS>1, WR assertion refers to the next rising edge of CLKOUT. "External Bus Synchronous Timings" should be used only for reference to the clock and not for relative timings. These timings are periodically sampled and are not 100% tested. Table 2-12 Address Trace Timings (Synchronous and Asynchronous) 60 MHz Num 250 251 252 253 Characteristics Address Setup Time to AT Assertion AT Pulse Width CLKOUT Low to AT Assertion CLKOUT Low to AT Deassertion * Minimum * Maximum 1. Expression Min 0.5 x TC - 4.4 0.5 x TC - 4.4 0.75 x TC + 5.5 0.25 x TC + 1.1 0.25 x TC + 5.5 3.9 3.9 18.0 5.3 -- Max -- -- -- -- 9.7 Unit ns ns ns ns ns Note: The Address Trace (AT) pin is also active on accesses to internal program memory if the Address Trace Enable (ATE) bit (Bit 15) of the OMR is set. In this case, the MCS, RD, and WR signals are deasserted and the data bus is tri-stated while the address bus is driven with the address of the internal access. 2-18 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics CLKOUT 198 A0-A15, MCS 252 AT 211 WR 210 203 D0-D23 208 RD 207 206 D0-D23 Data In AA0377 199 253 205 204 Data Out 202 209 Figure 2-13 Synchronous Bus Timings SRAM 1 WS AC Electrical Characteristics--Host Interface Timing (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) Host Port Usage Considerations Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the Host port. The considerations for proper operation are discussed below. 1. Asynchronous Reading of Receive Byte Registers--When reading the receive byte registers, RXH or RXL, the Host programmer should use MOTOROLA DSP56603/D, Preliminary 2-19 Specifications AC Electrical Characteristics interrupts or poll the RXDF flag, which indicates that data is available. This assures that the data in the receive byte registers will be valid. 2. Overwriting Transmit Byte Registers--The Host programmer should not write to the transmit byte registers, TXH or TXL, unless the TXDE bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers can transfer valid data to the HRX register. 3. Overwriting the Host Vector--The Host Vector register should be changed only when the Host Command bit (HC) is clear. This guarantees that the DSP56603 interrupt control logic can receive a stable vector. Table 2-13 Host Interface Timing 60 MHz Num 300 301 302 303 Characteristic Access Cycle Time Read Data Strobe Assertion Width5 HACK Assertion Width Read Data Strobe Deassertion Width5 HACK Deassertion Width Read Data Strobe Deassertion Width between two consecutive "Last Data Register" Reads, two consecutive CVR Reads, two consecutive ICR Reads, or two consecutive ISR Reads3, 5, 8 Write Data Strobe Assertion Width6 Write Data Strobe Deassertion Width6 HAS Assertion Width HAS Deassertion to Data Strobe Assertion4 Host Data Input Setup Time before Write Data Strobe Deassertion6 Host Data Input Hold Time after Write Data Strobe Deassertion6 Read Data Strobe Assertion to Output Data Active from High Impedance5, 10 HACK Assertion to Output Data Active from High Impedance 10 Read Data Strobe Assertion to Output Data Valid5 HACK Assertion to Output Data Valid Symbol -- -- -- -- Expression Min 4 x TC TC + 16.5 -- 2.5 x TC + 11.0 66.7 33.2 16.5 52.7 -- -- Max -- ns ns ns ns Unit 304 305 306 307 308 309 310 -- -- -- -- -- -- -- -- 2.5 x TC + 11.0 -- -- -- -- -- 22.0 52.7 16.5 0 16.5 5.5 5.0 -- -- -- -- -- -- -- ns ns ns ns ns ns ns 311 -- -- -- 33.0 ns 2-20 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics Table 2-13 Host Interface Timing (Continued) 60 MHz Num 312 Characteristic Read Data Strobe Deassertion to Output Data High Impedance5, 10 HACK Deassertion to Output Data High Impedance 10 Output Data Hold Time after Read Data Strobe Deassertion5 Output Data Hold Time after HACK Deassertion HCS Assertion to Read Data Strobe Deassertion HCS Assertion to Write Data Strobe Deassertion6 HCS Assertion to Output Data Valid HCS Hold Time after Data Strobe Deassertion4, 6 Address (HAD0-HAD7) Setup Time before HAS Deassertion (HMUX = 1) Address (HAD0-HAD7) Hold Time after HAS Deassertion (HMUX = 1) HA8-HA10 (HMUX = 1), HA0-HA2 (HMUX = 0), HRW Setup Time before Data Strobe Assertion4 HA8-HA10 (HMUX = 1), HA0-HA2 (HMUX = 0), HRW Hold Time after Data Strobe Deassertion4 Delay from Read Data Strobe Deassertion to Host Request Assertion for "Last Data Register" Read5, 7, 8, 9 Delay from Write Data Strobe Deassertion to Host Request Assertion for "Last Data Register" Write6, 7, 8, 9 Delay from Data Strobe Assertion to Host Request Deassertion for "Last Data Register" Read or Write (HROD = 0)4, 7, 8 Delay from Data Strobe Assertion to Host Request Deassertion for "Last Data Register" Read or Write (HROD = 1, Open drain host request) 4, 7, 8, 9 Symbol -- Expression Min -- -- Max 16.5 ns Unit 313 -- -- 5.5 -- ns 314 315 316 317 318 319 320 321 322 -- -- -- -- -- -- -- -- -- TC + 16.5 -- -- -- -- -- -- -- 2 x TC + 27.5 33.2 16.5 -- 0 7.7 5.5 11.0 5.5 60.8 -- -- 27.5 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns 323 -- 1.5 x TC + 27.5 52.5 -- ns 324 -- -- -- 27.5 ns 325 -- -- -- 300.0 ns MOTOROLA DSP56603/D, Preliminary 2-21 Specifications AC Electrical Characteristics Table 2-13 Host Interface Timing (Continued) 60 MHz Num Notes: 1. 2. Characteristic Symbol Expression Min Max Unit See Host Port Usage Considerations on page 2-19. In the following timing diagrams (Figure 2-14 through Figure 2-18), the controls pins are drawn as active low. Pin polarity is programmable. 3. This timing must be adhered to only if two consecutive reads from one of these registers are executed. 4. The Data Strobe is HRD or HWR in the Dual Data Strobe mode, HDS in the Single Data Strobe mode. 5. The Read Data Strobe is HRD in the Dual Data Strobe mode, HDS in the Single Data Strobe mode. 6. The Write Data Strobe is HWR in the Dual Data Strobe mode, HDS in the Single Data Strobe mode. 7. The Host Request is HREQ in the Single Host Request mode, HRRQ and HTRQ in the Double Host Request mode. 8. The "Last Data Register" is the register at address $7, which is the last location to be read or written in data transfers. 9. In this calculation, the host request signal is pulled up by a 4.7 k resistor in the Open Drain mode. 10. These timings are periodically sampled and are not 100% tested. HA0-HA2 320 314 HCS 300 301 HRD, HDS 316 311 312 310 HAD0-HAD7 324 325 HREQ HRRQ HTRQ 322 313 302 303 321 317 AA0378 Figure 2-14 Read Timing Diagram--Non Multiplexed Bus 2-22 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics HA0-HA2 320 315 317 HCS 300 304 HWD, HDS 308 309 HAD0-HAD7 324 HREQ HRRQ HTRQ 325 323 305 321 AA0379 Figure 2-15 Write Timing Diagram--Non Multiplexed Bus 300 301 HACK 302 311 303 310 313 HAD0-HAD7 312 HREQ AA0815 Figure 2-16 Host Interrupt Vector Register (IVR) Read Timing Diagram MOTOROLA DSP56603/D, Preliminary 2-23 Specifications AC Electrical Characteristics HA8-HA10 320 HCS 307 306 HRD, HDS 319 318 311 312 310 HAD0-HAD7 Address 324 325 HREQ HRRQ HTRQ 313 Data 322 302 303 301 300 321 AA0380 Figure 2-17 Read Timing Diagram--Multiplexed Bus 2-24 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics HA8-HA10 320 HAS 307 306 HWD, HDS 319 318 HAD0-HAD7 Address 324 325 HREQ HRRQ HTRQ 308 309 Data 323 305 304 300 AA0381 Figure 2-18 Write Timing Diagram--Multiplexed Bus AC Electrical Characteristics--SSI0/SSI1 Timing (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) Table 2-14 Key to Table 2-14 SSI Timing Case tSSICC TXC RXC FST FSR i ck SSI Clock Cycle Time Transmit Clock (on SCK Pin) Receive Clock (on SC0 or SCK Pin) Transmit Frame Sync (on SC2 Pin) Receive Frame Sync (SC1 or SC2 Pin) Internal Clock Meaning MOTOROLA DSP56603/D, Preliminary 2-25 Specifications AC Electrical Characteristics Table 2-14 Key to Table 2-14 SSI Timing (Continued) Case x ck i ck a i ck s bl wl wr External Clock Internal Clock, Asynchronous Mode (Asynchronous implies that TXC and RXC are two different clocks) Internal Clock, Synchronous Mode (Synchronous implies that TXC and RXC are the same clock) Bit Length Word Length Word Length Relative Meaning Table 2-15 SSI Timing 60 MHz Num Characteristics Symbol Expression Min 430 Clock Cycle 1 431 Clock High Period * for internal clock * for external clock 432 Clock Low Period * for internal clock * for external clock 433 RXC Rising Edge to FSR Out (bl) High 434 RXC Rising Edge to FSR Out (bl) Low 435 RXC Rising Edge to FSR Out (wr) High3 436 RXC Rising Edge to FSR Out (wr) Low3 437 RXC Rising Edge to FSR Out (wl) High 438 RXC Rising Edge to FSR Out (wl) Low tSSICC -- 4 x TC 3 x TC 2 x TC - 12.2 1.5 x TC 2 x TC - 12.2 1.5 x TC -- -- -- -- -- -- 66.7 50.0 21.1 25.0 21.1 25.0 -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 45.1 26.8 45.1 26.8 47.6 29.3 47.6 29.3 45.9 25.6 45.1 26.8 i ck x ck i ck x ck i ck x ck x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Case Unit -- -- -- -- -- -- -- 2-26 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics Table 2-15 SSI Timing (Continued) 60 MHz Num Characteristics Symbol Expression Min 439 Data In Setup Time before RXC (SCK in Synchronous Mode) Falling Edge 440 Data In Hold Time after RXC Falling Edge 441 FSR Input (bl, wr) High before RXC Falling Edge3 442 FSR Input (wl) High before RXC Falling Edge 443 FSR Input Hold Time after RXC Falling Edge 444 Flags Input Setup before RXC Falling Edge 445 Flags Input Hold Time after RXC Falling Edge 446 TXC Rising Edge to FST Out (bl) High 447 TXC Rising Edge to FST Out (bl) Low 448 TXC Rising Edge to FST Out (wr) High3 449 TXC Rising Edge to FST Out (wr) Low3 450 TXC Rising Edge to FST Out (wl) High 451 TXC Rising Edge to FST Out (wl) Low 452 TXC Rising Edge to Data Out Enable from High Impedance 454 TXC Rising Edge to Data Out Valid 455 TXC Rising Edge to Data Out High Impedance2 457 FST Input (bl, wr) Setup Time before TXC Falling Edge 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 + 0.5 x TC -- -- 0.0 23.2 6.1 3.6 28.0 1.2 28.0 1.2 3.6 0.0 0.0 23.2 7.3 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 21.0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35.4 18.3 37.8 20.7 37.8 20.7 40.3 23.2 36.6 19.5 37.8 20.7 37.8 20.7 52.8 25.6 37.8 19.5 -- -- x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Case Unit MOTOROLA DSP56603/D, Preliminary 2-27 Specifications AC Electrical Characteristics Table 2-15 SSI Timing (Continued) 60 MHz Num Characteristics Symbol Expression Min 458 FST Input (wl) to Data Out Enable from High Impedance2 460 FST Input (wl) Setup Time before TXC Falling Edge 461 FST Input Hold Time After TXC Falling Edge 462 Flag Output Valid After TXC Rising Edge Notes: 1. 2. 3. Case Unit Max 32.9 -- -- -- -- 39.0 22.0 x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns -- 2.0 21.0 4.0 0.0 -- -- -- -- -- -- -- -- -- -- For internal clock, External Clock Cycle is defined by Icyc and SSI control register. These timings are periodically sampled and are not 100% tested. The Word Relative Frame Sync signal is related to the clock signal as the Bit Length Frame Sync signal, but has a period that extends from one serial clock pulse prior to the first bit clock pulse (the same as the Bit Length Frame Sync signal) until one serial clock pulse prior to the last bit clock pulse of the first word in the frame. 2-28 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics 430 431 TXC (Input/Output) 446 FST (Bit) Out 450 FST (Word) Out 454 452 Data Out 457 FST (Bit) In 458 460 FST (Word) In 462 Flags Out NOTE: In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period. AA0382 432 447 451 454 455 First Bit Last Bit 461 461 Figure 2-19 SSI Transmitter Timing MOTOROLA DSP56603/D, Preliminary 2-29 Specifications AC Electrical Characteristics 430 431 RXC (Input/Output) 433 FSR (Bit) Out 437 FSR (Word) Out 439 Data In 441 FSR (Bit) In 443 440 First Bit Last Bit 438 434 432 442 FSR (Word) In 442 Flags In 443 445 AA0383 Figure 2-20 SSI Receiver Timing 2-30 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics AC Electrical Characteristics--Timer Timing (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) Table 2-16 Timer Timing 60 MHz Num 480 481 482 483 Characteristics Symbol -- -- -- -- Expression Min TIO Low TIO High Timer Setup Time from TIO (Input) Assertion to CLKOUT Rising Edge Synchronous Timer Delay Time from CLKOUT Rising Edge to the External Memory Access Address Out Valid, caused by first interrupt instruction execution CLKOUT Rising Edge to TIO (output) Assertion CLKOUT Rising Edge to TIO (output) Deassertion 2 x TC + 2.4 2 x TC + 2.4 TC 10.25 x TC + 1.2 35.7 35.7 11.0 172.0 Max -- -- 16.7 -- ns ns ns ns Unit 484 485 -- -- 0.5 x TC + 4.3 0.5 x TC + 24.2 0.5 x TC + 4.3 0.5 x TC + 24.2 12.6 12.6 32.5 32.5 ns ns TIO 480 481 AA0384 Figure 2-21 TIO Timer Event Input Restrictions MOTOROLA DSP56603/D, Preliminary 2-31 Specifications AC Electrical Characteristics CLKOUT TIO (Input) 482 Address 483 First Interrupt Instruction Execution AA0493 Figure 2-22 Timer Interrupt Generation CLKOUT TIO (Output) 484 485 AA0494 Figure 2-23 External Pulse Generation 2-32 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics AC Electrical Characteristics--GPIO Timing (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) Note: GPIO timings apply to all GPIO signals used on the dedicated GPIO pins, HI08 pins, SSI pins, and Timer pins. Table 2-17 GPIO Timing 60 MHz Num Characteristics Symbol Expression Min 490 491 492 493 494 CLKOUT Edge to GPIO Output Valid (GPIO Out Delay Time) CLKOUT Edge to GPIO Output Invalid (GPIO Out Hold Time) GPIO In Valid to CLKOUT Edge (GPIO In Setup Time) CLKOUT Edge to GPIO Input Invalid (GPIO In Hold Time) Fetch to CLKOUT Edge before GPIO Change -- -- -- -- -- -- -- -- -- 6.75 x TC -- 3.6 14.6 0.0 112.5 Max 37.8 -- -- -- -- ns ns ns ns ns Unit CLKOUT (Output) 490 491 GPIO (Output) 492 GPIO (Input) Valid 493 A0-A15 494 fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register AA0384 Figure 2-24 GPIO Timing MOTOROLA DSP56603/D, Preliminary 2-33 Specifications AC Electrical Characteristics AC Electrical Characteristics--JTAG Timing (VCC = 3.0 V 0.3 V; TA = -40 to 85C, CL = 50 pF + 2 TTL Loads) Table 2-18 JTAG Timing 60 MHz Num 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 Characteristics Symbol -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Expression Min TCK Frequency of Operation TCK Cycle Time in Crystal Mode TCK Clock Pulse Width Measured at 1.5 V TCK Rise and Fall Times Boundary Scan Input Data Setup Time Boundary Scan Input Data Hold Time TCK Low to Output Data Valid TCK Low to Output High Impedance1 TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO High Impedance1 TRST Assert Time TRST Setup Time to TCK Low DE assertion time in order to enter debug mode Response time when DSP56603 is executing NOP instructions from internal memory Debug acknowledge assertion time 1. Unit Max 22.0 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0 -- -- -- 124.7 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0 25.0 0.0 0.0 100.0 40.0 36.0 -- 1/(3 x TC) -- -- -- -- -- -- -- -- -- -- -- -- -- 1.5 x TC + 11.0 5.5 x TC + 33.0 516 Note: 3 x TC + 11.0 61.0 -- ns These timings are periodically sampled and are not 100% tested. 2-34 DSP56603/D, Preliminary MOTOROLA Specifications AC Electrical Characteristics 501 502 TCK (Input) VIH 503 VM VIL 503 502 VM AA0496 Figure 2-25 Test Clock Input Timing Diagram TCK (Input) VIL 504 VIH 505 Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs Input Data Valid Output Data Valid Output Data Valid AA0497 Figure 2-26 Boundary Scan (JTAG) Timing Diagram MOTOROLA DSP56603/D, Preliminary 2-35 Specifications AC Electrical Characteristics TCK (Input) TDI TMS (Input) VIL 508 VIH 509 Input Data Valid 510 TDO (Output) 511 TDO (Output) 510 TDO (Output) Output Data Valid Output Data Valid AA0498 Figure 2-27 Test Access Port Timing Diagram TCK (Input) 513 TRST (Input) 512 AA0499 Figure 2-28 TRST Timing Diagram DE 514 515 516 AA0500 Figure 2-29 OnCE--Debug Request 2-36 DSP56603/D, Preliminary MOTOROLA PACKAGING PACKAGE AND PIN-OUT INFORMATION This section contains package and pin-out information for the 144-pin Thin Quad Flat Pack (TQFP) configuration of the DSP56603. Table 3-1 on page 3-4 identifies the DSP56603 pins on the package in numeric order. Table 3-2 on page 3-5 identifies the DSP56603 pins by name order. Table 3-4 on page 3-11 groups power and ground leads. Mechanical drawings of the package are presented in Figure 3-3 on page 3-12. Complete mechanical information regarding DSP56603 packaging is available by facsimile through Motorola's MfaxTM system. Call (602) 244-6609 to obtain instructions for using this system. The automated system requests the following information: * * The receiving fax telephone number including area code or country code The caller's Personal Identification Number (PIN) Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. * The type of information requested: - - - - Instructions for using the system A literature order form Specific part technical information or data sheets Other information described by the system messages A total of three documents may be ordered per call. Packaging Package and Pin-Out Information 108 D7 D8 VCCD GNDD D9 D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19 VCCQL GNDQ D20 VCCD GNDD D21 D22 D23 MODD MODC MODB MODA TRST TDO TDI TCK TMS SC12 SC11 73 D6 D5 D4 D3 GNDD VCCD D2 D1 D0 nc nc A15 GNDA VCCQH A14 A13 A12 VCCQL GNDQ A11 A10 GNDA VCCA A9 A8 A7 A6 GNDA VCCA A5 A4 A3 A2 GNDA VCCA A1 109 72 Orientation Mark Notes: 1. 2. Figure 3-1 Top View of DSP56603 144-pin Plastic Thin Quad Flat Package 3-2 SRD1 STD1 SC02 SC01 DE PINIT/NMI SRD0 VCCS GNDS STD0 SC10 SC00 GPIO0 GPIO1 GPIO2 SCK1 SCK0 VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HREQ/HTRQ VCCS GNDS TIO2 TIO1 TIO0 HCS/HA10 HA2/HA9 HA1/HA8 HA0/HAS HAD7 HAD6 HAD5 Pins marked "nc" are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. To simplify locating the pins, each fifth pin is shaded in the illustration. DSP56603/D, Preliminary 36 1 144 (Top View) 37 A0 nc MCS nc RD WR GNDC VCCC nc nc nc nc AT CLKOUT GNDC VCCQH VCCQL EXTAL GNDQ XTAL nc nc nc nc GNDP1 GNDP PCAP VCCP RESET HAD0 HAD1 HAD2 HAD3 GNDH VCCH HAD4 MOTOROLA Packaging Package and Pin-Out Information Notes: 1. 2. Figure 3-2 Bottom View of DSP56603 144-pin Plastic Thin Quad Flat Package MOTOROLA HAD5 HAD6 HAD7 HA0/HAS HA1/HA8 HA2/HA9 HCS/HA10 TIO0 TIO1 TIO2 GNDS VCCS HREQ/HTRQ HACK/HRRQ HRW/HRD HDS/HWR VCCQH GNDQ VCQCL SCK0 SCK1 GPIO2 GPIO1 GPIO0 SC00 SC10 STD0 GNDS VCCS SRD0 PINIT/NMI DE SC01 SC02 STD1 SRD1 Pins marked "nc" are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. To simplify locating the pins, each fifth pin is shaded in the illustration. DSP56603/D, Preliminary 1 A0 nc MCS nc RD WR GNDC VCCC nc nc nc nc AT CLKOUT GNDC VCCQH VCCQL EXTAL GNDQ XTAL nc nc nc nc GNDP1 GNDP PCAP VCCP RESET HAD0 HAD1 HAD2 HAD3 GNDH VCCH HAD4 A1 VCCA GNDA A2 A3 A4 A5 VCCA GNDA A6 A7 A8 A9 VCCA GNDA A10 A11 GNDQ VCCQL A12 A13 A14 VCCQH GNDA A15 nc nc D0 D1 D2 VCCD GNDD D3 D4 D5 D6 109 Orientation Mark (on Top side) 37 (Bottom View) D7 D8 VCCD GNDD D9 D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19 VCCQL GNDQ D20 VCCD GNDD D21 D22 D23 MODD MODC MODB MODA TRST TDO TDI TCK TMS SC12 SC11 73 3-3 Packaging Package and Pin-Out Information Table 3-1 DSP56603 144-pin TQFP Pin Identification by Pin Number UP Pin # 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Name SC11 SC12 TMS TCK TDI TDO TRST MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD D23 D22 D21 GNDD VCCD D20 GNDQ VCCQL D19 D18 D17 D16 D15 GNDD VCCD D14 D13 D12 D11 D10 D9 GNDD VCCD D8 D7 RIGHT Pin # 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Name D6 D5 D4 D3 GNDD VCCD D2 D1 D0 nc nc A15 GNDA VCCH A14 A13 A12 VCCQL GNDQ A11 A10 GNDA VCCA A9 A8 A7 A6 GNDA VCCA A5 A4 A3 A2 GNDA VCCA A1 DOWN Pin # 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Name A0 nc MCS nc RD WR GNDC VCCC nc nc nc nc AT CLKOUT GNDC VCCQH VCCLQ EXTAL GNDQ XTAL nc nc nc nc GNDP1 GNDP PCAP VCCP RESET HAD0 HAD1 HAD2 HAD3 GNDH VCCH HAD4 Pin # 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LEFT Name HAD5 HAD6 HAD7 HA0/HAS HA1/HA8 HA2/HA9 HCS/HA10 TIO0 TIO1 TIO2 GNDS VCCS HREQ/HTRQ HACK/HRRQ HRW/HRD HDS/HWR VCCQH GNDQ VCCQL SCK0 SCK1 GPIO2 GPIO1 GPIO0 SC00 SC10 STD0 GNDS VCCS SRD0 PINIT/NMI DE SC01 SC02 STD1 SRD1 Note: Pins marked "nc" in Table 3-1 are not connected. 3-4 DSP56603/D, Preliminary MOTOROLA Packaging Package and Pin-Out Information Table 3-2 DSP56603 144-pin TQFP Pin Identification by Pin Name Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 AT CLKOUT D0 D1 D2 D3 D4 D5 D6 D7 Pin # 72 73 76 77 78 79 82 83 84 85 88 89 92 93 94 97 60 59 100 101 102 105 106 107 108 109 Port A Control Clock/PLL Port A Data Functional Group Port A Address Name D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 DE EXTAL GNDA GNDA GNDA GNDA GNDC GNDC GNDD GNDD Pin # 110 113 114 115 116 117 118 121 122 123 124 125 128 131 132 133 5 55 75 81 87 96 66 58 104 112 GND--Port A Data GND--Port A Control GND--Port A Address JTAG/OnCE Functional Group Port A Data MOTOROLA DSP56603/D, Preliminary 3-5 Packaging Package and Pin-Out Information Table 3-2 DSP56603 144-pin TQFP Pin Identification by Pin Name (Continued) Name GNDD GNDD GNDH GNDP GNDP1 GNDQ GNDQ GNDQ GNDQ GNDS GNDS GPIO0 GPIO1 GPIO2 HA0/HAS HA1/HA8 HA2/HA9 HACK/HRRQ HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 Pin # 120 130 39 47 48 19 54 90 127 9 26 13 14 15 33 32 31 23 43 42 41 40 37 36 35 34 Peripherals/HI08 GND--SSI, Timer, GPIO, HI08 Control Peripherals/GPIO Quiet GND (for both VCCQH and VCCQL) GND--HI08 Data GND--PLL Functional Group GND--Port A Data Name HCS/HA10 HDS/HWR HREQ/HTRQ HRW/HRD MCS MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD PCAP PINIT/NMI RD RESET SC00 SC01 SC02 SC10 SC11 SC12 SCK0 SCK1 SRD0 SRD1 STD0 STD1 TCK Pin # 30 21 24 22 70 137 136 135 134 46 6 68 44 12 4 3 11 144 143 17 16 7 1 10 2 141 Peripherals/SSI0 Peripherals/SSI1 Peripherals/SSI0 Peripherals/SSI1 Peripherals/SSI0 Peripherals/SSI1 JTAG/OnCE Peripherals/SSI1 Peripherals/SSI0 Port A Control Clock/PLL Port A Control Mode/Interrupt Control Functional Group Peripherals/HI08 3-6 DSP56603/D, Preliminary MOTOROLA Packaging Package and Pin-Out Information Table 3-2 DSP56603 144-pin TQFP Pin Identification by Pin Name (Continued) Name TDI TDO TIO0 TIO1 TIO2 TMS TRST VCCA VCCA VCCA VCCC VCCD VCCD VCCD VCCD Pin # 140 139 29 28 27 142 138 74 80 86 65 103 111 119 129 VCC--Port A Control VCC--Port A Data VCC--Port A Address JTAG/OnCE Peripherals/Timer Functional Group JTAG/OnCE Name VCCH VCCP VCCQH VCCQH VCCQH VCCQL VCCQL VCCQL VCCQL VCCS VCCS WR XTAL nc Pin # 38 45 20 57 95 18 56 91 126 8 25 67 53 VCC --SSI, Timer, GPIO, HI08 Control Port A Control Clock/PLL Quiet VCC Low Functional Group VCC--HI08 Data VCC--PLL Quiet VCC High 49,50,51,52,61, 62, 63, 64, 69, 71, 98, 99 Note: The 12 pins marked as "nc" are reserved for possible future enhancements. Do not connect these pins to any power, signal, or ground traces or vias. MOTOROLA DSP56603/D, Preliminary 3-7 Packaging Package and Pin-Out Information Table 3-3 DSP56603 Functional Signal Groups (144 TQFP) Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Pin # 72 73 76 77 78 79 82 83 84 85 88 89 92 93 94 97 100 101 102 105 106 107 108 109 110 113 Core/Port A Data Functional Group Core/Port A Address D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 AT MCS MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RD WR VCCA VCCA VCCA VCCC Name Pin # 114 115 116 117 118 121 122 123 124 125 128 131 132 133 60 70 137 136 135 134 68 67 74 80 86 65 Core/VCC Port A Ctrl Core/VCC Port A Address Core/Port A Ctrl Functional Group Core/Port A Data 3-8 DSP56603/D, Preliminary MOTOROLA Packaging Package and Pin-Out Information Table 3-3 DSP56603 Functional Signal Groups (144 TQFP) (Continued) Name VCCD VCCD VCCD VCCD GNDA GNDA GNDA GNDA GNDC GNDC GNDD GNDD GNDD GNDD CLKOUT EXTAL PCAP PINIT/NMI XTAL VCCP GNDP GNDP1 DE TCK TDI TDO Pin # 103 111 119 129 75 81 87 96 58 66 104 112 120 130 59 55 46 6 53 45 47 48 5 141 140 139 Core/JTAG Core/VCC for PLL Core/GND for PLL Core/PLL Core/GND Port A Control Core/GND for Port A Data Core/GND for Port A Address Functional Group Core/VCC for Port A Data Name TMS TRST HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HA0/HAS HA1/HA8 HA2/HA9 HCS/HA10 HACK/HRRQ HDS/HWR HREQ/HTRQ HRW/HRD VCCH GNDH SC00 SC01 SC02 SCK0 SRD0 STD0 Pin # 142 138 43 42 41 40 37 36 35 34 33 32 31 30 23 21 24 22 38 39 12 4 3 17 7 10 Peripherals/VCC HI08 Peripherals/GND HI08 Peripherals/SSI0 Peripherals/HI08 Functional Group Core/JTAG MOTOROLA DSP56603/D, Preliminary 3-9 Packaging Package and Pin-Out Information Table 3-3 DSP56603 Functional Signal Groups (144 TQFP) (Continued) Name SC10 SC11 SC12 SCK1 SRD1 STD1 TIO0 TIO1 TIO2 GPIO0 GPIO1 GPIO2 VCCS VCCS Pin # 11 144 143 16 1 2 29 28 27 13 14 15 8 25 Peripherals/VCC for SSI0, SSI1, TIMER, GPIO Peripherals/GPIO Peripherals/Timer Functional Group Peripherals/SSI1 Name GNDS GNDS VCCQH VCCQH VCCQH VCCQL VCCQL VCCQL VCCQL GNDQ GNDQ GNDQ GNDQ nc Pin # 9 26 20 57 95 18 56 91 126 19 54 90 127 49, 50, 51, 52, 61, 62, 63, 64, 69, 71, 98, 99 Quiet Ground (for both VCCQH and VCCQL) Quiet VCC Low Functional Group Peripherals/GND for SSI0, SSI1, Timer, GPIO Quiet VCC High Note: The 12 pins marked as "nc" are reserved for possible future enhancements. Do not connect these pins to any power, signal, or ground traces or vias. Power and ground pins have special considerations for noise immunity. See Electrical Design Considerations, on page 4-3, for more information. 3-10 DSP56603/D, Preliminary MOTOROLA Packaging Package and Pin-Out Information Table 3-4 DSP56603 144-pin TQFP Power Supply Pins Name VCCA VCCA VCCA GNDA GNDA GNDA GNDA VCCC GNDC GNDC VCCQH VCCQH VCCQH VCCLQ VCCQL VCCQL VCCQL GNDS GNDS Pin # 74 80 86 75 81 87 96 65 66 58 20 57 95 18 56 91 126 9 26 Peripherals/SSI0, SSI1, Timer, GPIO, HI08 Control Quiet VCC Low Quiet VCC High Core/Port A Control Functional Group Core/Port A Address Name VCCD VCCD VCCD VCCD GNDD GNDD GNDD GNDD VCCP GNDP GNDP1 GNDQ GNDQ GNDQ GNDQ VCCH GNDH VCCS VCCS Pin # 103 111 119 129 104 112 120 130 45 47 48 19 54 90 127 38 39 8 25 Peripherals/SSI0, SSI1, Timer, GPIO, HI08 Control Peripherals/HI08 Data Quiet GND (for both VCCQH and VCCQL) Core/PLL Functional Group Core/Port A Data MOTOROLA DSP56603/D, Preliminary 3-11 Packaging Package and Pin-Out Information 4X 0.20 T L-M N 4X 36 TIPS 0.20 T L-M N PIN 1 IDENT 144 109 1 108 J1 J1 L M B V 140X 4X P C L X X=L, M OR N G VIEW Y 36 73 B1 V1 VIEW Y 37 72 N A1 S1 A S VIEW AB C 2 0.1 T 144X NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5-1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCULDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLED DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.35. SEATING PLANE 2 T PLATING J F AA C2 -- 0.05 R2 R1 D 0.08 M T L-M N SECTION J1-J1 (ROTATED 90) 144 PL BASE METAL 0.25 GAGE PLANE (K) C1 (Y) E VIEW AB (Z) 1 DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 MILLIMETERS MIN MAX 20.00 BSC 10.00 BSC 20.00 BSC 10.00 BSC 1.40 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.45 0.75 0.17 0.23 0.50 BSC 0.09 0.20 0.50 REF 0.25 BSC 0.13 0.20 0.13 0.20 22.00 BSC 11.00 BSC 22.00 BSC 11.00 BSC 0.25 REF 1.00 REF 0.09 0.16 0 -- 0 7 11 13 CASE 918-03 Figure 3-3 144-pin Thin Quad Flat Pack (TQFP) Mechanical Information 3-12 DSP56603/D, Preliminary MOTOROLA SECTION 4 DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: T J = T A + ( P D x R JA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-tocase thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. Again, MOTOROLA DSP56603/D, Preliminary 4-1 Design Considerations Thermal Design Considerations if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: * Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ - TT)/PD where TT is the temperature of the package case determined by a thermocouple. * * As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or JT, has been defined to be (TJ -TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. Note: Table 2-3 Package Thermal Characteristics on page 2-2 contains the package thermal values for this chip. 4-2 DSP56603/D, Preliminary MOTOROLA Design Considerations Electrical Design Considerations ELECTRICAL DESIGN CONSIDERATIONS CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Each VCC pin on the DSP56603 should be provided with a low-impedance path to the board's supply. Each GND pin should likewise be provided with a lowimpedance path to ground. The power supply pins drive distinct groups of logic on-chip as shown in Table 1-2 Power Inputs on page 1-3 and Table 1-3 Grounds on page 1-4. For best results, separate VCC and GND for each supply is recommended; each with a capacitor to bypass VCC to GND as close as possible to the package. Otherwise, a multi-layer board is recommended, employing two inner layers as VCC and GND planes. Two 0.1 F ceramic capacitors as close as possible to each side of the package (eight capacitors altogether) should be used to bypass the VCC power supply layer to the ground layer. In such cases, there is no separation between the various power and ground supplies, since each one is directly tied to the appropriate plane. Therefore, the capacitors are common to all the VCC/GND pairs. The VCC/GND supplies of the PLL should be well-regulated (non-switching regulators), and the pins should be provided with an extremely low impedance path to VCC/GND. It is recommended that VCCP should be connected to the main power supply with a special power branch. If required, filtering circuitry should be provided. If VCCP and GNDP are kept separate from the other supplies, an additional larger capacitor (e.g., 47 F) should be used between these pins. An additional large capacitor should be placed next to the power supply itself. MOTOROLA DSP56603/D, Preliminary 4-3 Design Considerations Electrical Design Considerations All output pins on the DSP56603 have fast rise and fall times. Printed Circuit Board (PCB) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses, as well as to the Port A control signals and Port B pins. Maximum PCB trace lengths on the order of 6 inches (15.24 cm) are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Drive to a valid value (e.g., connect to pull-up or pull-down resistors) all unused inputs or signals that will be inputs during reset (RESET asserted). Every input pin should be driven to a valid value after the RESET deassertion by connecting it to a pull-up or pull-down resistor if not used. Exceptions to this are the TRST, DE, and TMS pins, which have internal pull-up resistors. The RESET and TRST pins must be asserted low after power-up. All this data relates to a single DSP56603. If multiple DSP56603 devices are on the same board, check for cross-talk or excessive spikes on the supplies caused by synchronous operation of the devices. 4-4 DSP56603/D, Preliminary MOTOROLA Design Considerations Power Consumption Considerations POWER CONSUMPTION CONSIDERATIONS Power dissipation is a key issue in portable DSP applications. This section describes some of the factors that affect current consumption. Most of the current consumed by CMOS devices is Alternating Current (AC), which is charging and discharging the capacitances of the pins and internal nodes. Therefore, the total current consumption is the sum of these internal and external currents. This current consumption is described by the formula: Equation 3: I = C x V x f where: C = node/pin capacitance (in Farads) V = voltage swing (in volts) f = frequency of node/pin toggle (in Hz) Example 4-1 Current Consumption For a Port A address pin loaded with 50 pF capacitance, operating at 2.7 V, and with a 60 MHz clock, toggling at its maximum possible rate of 15 MHz, the current consumption is (for this pin only): Equation 4: I = 50 x 10-12 x 2.7 x 15 x 106 = 2.025 mA The Typical Internal Current value (ICCI) reflects the typical switching of the internal buses in a typical DSP-intensive application. For applications requiring very low current consumption, it is recommended to: * * * * * * * * Set the PCD bit (in the OMR) and do not use the PC-relative instructions. Set the EBD bit (in the OMR) when not accessing external memory Minimize external memory accesses and use internal memory accesses instead Minimize the number of pins that are switching Minimize the capacitive load on the pins Connect the unused inputs to pull-up or pull-down resistors. Disable unused peripherals Disable unused pin activity (e.g., CLKOUT, XTAL) A common way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm and MOTOROLA DSP56603/D, Preliminary 4-5 Design Considerations PLL Performance Issues measure the current consumption at two different frequencies, F1 and F2. Then use the following equation to derive the current per MIPS value: Equation 5: I MIPS = I MHz = ( I typF2 - I typF1 ) ( F2 - F1 ) where: ItypF2 = current at F2 ItypF1 = current at F1 F2 = high frequency (any specified operating frequency) F1 = low frequency (any specified operating frequency lower than F2) Note: F1 should be significantly less than F2. For example, F2 could be 60 MHz and F1 could be 30 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. PLL PERFORMANCE ISSUES The following explanations are provided as general observations on expected PLL behavior. Measurements are preliminary and are subject to change. Phase Skew Performance The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. For input frequencies greater than 15 MHz and MF 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between -1.4 ns and +3.2 ns. Phase Jitter Performance The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than 2 ns. 4-6 DSP56603/D, Preliminary MOTOROLA Design Considerations PLL Performance Issues FREQUENCY JITTER PERFORMANCE The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 2-3%. INPUT (EXTAL) JITTER REQUIREMENTS The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then the allowed jitter can be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. MOTOROLA DSP56603/D, Preliminary 4-7 Design Considerations PLL Performance Issues 4-8 DSP56603/D, Preliminary MOTOROLA SECTION 5 ORDERING INFORMATION Table 5-1 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 5-1 DSP56603 Ordering Information Part DSP56603 Supply Voltage 3.0 V Package Type Plastic Thin Quad Flat Pack (TQFP) Pin Count 144 Frequency (MHz) 60 Order Number DSP56603PV60 MOTOROLA DSP56603/D, Preliminary 5-1 Ordering Information 5-2 DSP56603/D, Preliminary MOTOROLA APPENDIX A POWER CONSUMPTION BENCHMARK The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL. Then it disables the XTAL generation, external CLKOUT generation, external port, and PC-relative instructions. Finally it uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation. This synthetic benchmark provides a structure and performance that is similar to a typical DSP-intensive algorithm, as used in the target cellular subscriber market. A typical target application consumes approximately 90% of the current used by this benchmark program. The two listed equate files, ioequ.asm and intequ.asm, are available in print format in Appendix B of the DSP56603 User's Manual, DSP56603UM/AD, as well as electronically via the Internet on the Motorola DSP home page. The web page address is provided on the back page of this document. INT_PROG INT_XDAT INT_YDAT equ equ equ $0 $0 $0 ; ; ; ; ; Internal starting Internal starting INTERNAL program memory address X-data memory address Y-data memory INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org movep P:INT_PROG #$d0,x:M_PCTL1 ; ; ; ; ; XTAL disable PLL enable CLKOUT disable set EBD set PCD ori ori PROG_START move move move move clr clr #$10,omr #$20,omr #$0,r0 #$0,r4 #$3f,m0 #$3f,m4 a b MOTOROLA DSP56603/D, Preliminary A-1 Power Consumption Benchmark move move move move do mac mac add mac mac move _end nop nop org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc #$0,x0 #$0,x1 #$0,y0 #$0,y1 forever, _end x0,y0,a x1,y1,a a,b x0,y0,a x1,y1,a b1,x:$ff ; Main Loop y:(r4)+,y1 y:(r4)+,y0 x:(r0)+,x1 x:(r0)+,x0 x:(r0)+,x1 y:(r4)+,y0 x:XDAT_START $2EB9 $F2FE $6A5F $6CAC $FD75 $10A $6D7B $A798 $FBF1 $63D6 $6657 $A544 $662D $E762 $F0F3 $F1B0 $829 $F7AE $A94F $78DC $2DE5 $E0BA $AB6B $26C8 $361 $6E86 $7347 $E774 $349D $ED12 $FCE3 $26E0 $7D99 $A85E $A43F A-2 DSP56603/D, Preliminary MOTOROLA Power Consumption Benchmark dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc $B10C $A55 $EC6A $255B $F1F8 $26D1 $6536 $BC37 $35A4 $F0D $BEC2 $E4D3 $E810 $F09 $E50E $FB2F $753C $62C5 $641A $3B4B $A928 $6641 $A7E6 $2127 $2FD4 $57D $3C72 $8C3 $7540 y:YDAT_START $6DA $F70B $39E8 $E801 $66A6 $F8E7 $EC94 $233D $2732 $3C83 $3E00 $B639 $A47E $FDDF $A2C $7CF5 $6A8A $B8FB $ED18 $F371 $A556 $E9D7 MOTOROLA DSP56603/D, Preliminary A-3 Power Consumption Benchmark dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc $A2C4 $35AD $E0E2 $2C73 $2730 $7FA9 $292E $3CCF $A65C $6D65 $A3A $B6EB $AC48 $7AE1 $3006 $F6C7 $64F4 $E41D $2692 $3863 $BC60 $A519 $39DE $F7BF $3E8C $79D5 $F5EA $30DB $B778 $FE51 $A6B6 $FFB7 $F324 $2E8D $7842 $E053 $FD90 $2689 $B68E $2EAF $62BC $A245 ; End of program A-4 DSP56603/D, Preliminary MOTOROLA OnCE and Mfax are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/ Affirmative Action Employer. How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 20912 Phoenix, Arizona 85036 1 (800) 441-2447 or 1 (602) 303-5454 Mfax: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-2662928 Technical Resource Center: 1 (800) 521-6274 DSP Helpline dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Japan: Nippon Motorola Ltd. Tatsumi-SPD-JLDC 6F Seibu-Butsuryu-Center 3-14-2 Tatsumi Koto-Ku Tokyo 135, Japan 03-3521-8315 |
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